发明名称 |
METHOD AND APPARATUS FOR GENERATING FLAGS FOR A PROCESSOR |
摘要 |
A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.
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申请公布号 |
US2013166889(A1) |
申请公布日期 |
2013.06.27 |
申请号 |
US201113334286 |
申请日期 |
2011.12.22 |
申请人 |
AREKAPUDI SRIKANTH;GUPTA SAURABH;ADVANCED MICRO DEVICES, INC. |
发明人 |
AREKAPUDI SRIKANTH;GUPTA SAURABH |
分类号 |
G06F9/315;G06F9/302;G06F9/305;G06F9/38 |
主分类号 |
G06F9/315 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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