发明名称 SCAN FLIP-FLOP AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a scan flip-flop that performs scan shift operation normally with either a positive edge or a negative edge of a clock signal. <P>SOLUTION: The scan flip-flop includes a master latch which holds or does not hold and outputs a received data signal or scan test signal in synchronism with the clock signal according to a scan enable signal, and a slave latch which holds or does not hold and outputs a signal received from the master latch in synchronism with the scan enable signal and clock signal, the scan enable signal varying from a first level to a second level before a pulse wave included in the clock signal rises and varying from the second level to the first level after the pulse wave rises, and varying from the first level to the second level before the pulse wave falls and varying from the second level to the first level after the pulse wave falls. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013127396(A) 申请公布日期 2013.06.27
申请号 JP20110276852 申请日期 2011.12.19
申请人 RENESAS ELECTRONICS CORP 发明人 HATANAKA HIROYUKI
分类号 G01R31/28;H03K3/037;H03K3/3562 主分类号 G01R31/28
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