摘要 |
Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers. |
申请人 |
INTEL CORPORATION;KRISHNAMURTHY, HARISH, K.;PRATT, ANNABELLE;NEIDENGARD, MARK, L.;MATTHEW, GEORGE, E.;DARNES, JAMES, ALEXANDER |
发明人 |
KRISHNAMURTHY, HARISH, K.;PRATT, ANNABELLE;NEIDENGARD, MARK, L.;MATTHEW, GEORGE, E.;DARNES, JAMES, ALEXANDER |