摘要 |
<p>Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.</p> |
申请人 |
INTEL CORPORATION;RADOSAVLJEVIC, MARKO;PILLARISETTY, RAVI;DEWEY, GILBERT;MUKHERJEE, NILOY;KAVALIEROS, JACK;RACHMADY, WILLY;LE, VAN;CHU-KUNG, BENJAMIN;METZ, MATTHEW V.;CHAU, ROBERT |
发明人 |
RADOSAVLJEVIC, MARKO;PILLARISETTY, RAVI;DEWEY, GILBERT;MUKHERJEE, NILOY;KAVALIEROS, JACK;RACHMADY, WILLY;LE, VAN;CHU-KUNG, BENJAMIN;METZ, MATTHEW V.;CHAU, ROBERT |