A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.
申请公布号
US2013162312(A1)
申请公布日期
2013.06.27
申请号
US201213679045
申请日期
2012.11.16
申请人
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONS;INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人
JUNG SEONGOOK;PARK JUNG-HYUN;RYU KYUNG HO;JUNG DONG HUN