APPARATUS AND METHOD OF IMPROVED PERMUTE INSTRUCTIONS
摘要
An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
申请公布号
WO2013095637(A1)
申请公布日期
2013.06.27
申请号
WO2011US67210
申请日期
2011.12.23
申请人
INTEL CORPORATION;OULD-AHMED-VALL, ELMOUSTAPHA;VALENTINE, ROBERT;CORBAL, JESUS;TOLL, BRET L.;CHARNEY, MARK J.
发明人
OULD-AHMED-VALL, ELMOUSTAPHA;VALENTINE, ROBERT;CORBAL, JESUS;TOLL, BRET L.;CHARNEY, MARK J.