| 摘要 |
Disclosed herein is a semiconductor chip that includes:
a plurality of penetration electrodes (15) each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and
a third penetration electrode; and a wiring (18) configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode. |
