发明名称 |
Semiconductor device, control method for the semiconductor device and information processing system including the same |
摘要 |
The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.
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申请公布号 |
US8473653(B2) |
申请公布日期 |
2013.06.25 |
申请号 |
US20100923714 |
申请日期 |
2010.10.05 |
申请人 |
KONDO CHIKARA;NISHIOKA NAOHISA;ELPIDA MEMORY, INC. |
发明人 |
KONDO CHIKARA;NISHIOKA NAOHISA |
分类号 |
G06F3/00;G06F13/12;G06F13/38 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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