发明名称 |
On-chip leakage current modeling and measurement circuit |
摘要 |
At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
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申请公布号 |
US8473879(B2) |
申请公布日期 |
2013.06.25 |
申请号 |
US201213484868 |
申请日期 |
2012.05.31 |
申请人 |
JOSHI RAJIV V.;KANJ ROUSAIDA N.;KUANG JENTE B.;NASSIF SANI R.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JOSHI RAJIV V.;KANJ ROUSAIDA N.;KUANG JENTE B.;NASSIF SANI R. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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