发明名称 |
Data processing circuit with multiplexed memory |
摘要 |
A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted.
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申请公布号 |
US8473706(B2) |
申请公布日期 |
2013.06.25 |
申请号 |
US201213481914 |
申请日期 |
2012.05.28 |
申请人 |
KESSELS JOZEF LAURENTIUS WILHELMUS;ANDREJIC IVAN;CALLAHAN CELLULAR L.L.C. |
发明人 |
KESSELS JOZEF LAURENTIUS WILHELMUS;ANDREJIC IVAN |
分类号 |
G06F12/00;G06F13/16 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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