| 摘要 |
Implementations of the present disclosure involve an apparatus and/or method for identifying and classify nodes of an electrical circuit design to account for hold time violations occurring within the circuit. The nodes may be ordered based on a criticality of the nodes that may aid in identifying those nodes of the circuit where hold time violations may be corrected. In one embodiment, the criticality may relate to the number of potentially violating paths that utilize the identified nodes such that corrective measures applied at those nodes may correct several hold time violating paths. In addition, criticality may be scaled utilizing an available buffer library and other timing information. Thus, by utilizing the methods and/or apparatuses of the present disclosure, the locations where timing violation corrective measures may be applied that improve or correct several violating data paths at once may be identified in such a manner so as to reduce the number of overall corrections made to the circuit design, reducing the cost and necessary time associated with the corrections.
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