发明名称 |
Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge |
摘要 |
An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
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申请公布号 |
US8471744(B1) |
申请公布日期 |
2013.06.25 |
申请号 |
US201113308737 |
申请日期 |
2011.12.01 |
申请人 |
WAN HO MING (KAREN);WONG YAT TO (WILLIAM);CHAN KWAI CHI;HONG KONG APPLIED SCIENCE & TECHNOLOGY RESEARCH INSTITUTE COMPANY, LTD. |
发明人 |
WAN HO MING (KAREN);WONG YAT TO (WILLIAM);CHAN KWAI CHI |
分类号 |
H03M3/00 |
主分类号 |
H03M3/00 |
代理机构 |
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