Semiconductor device having hierarchical bit line structure

摘要

A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches. In a first period, each sense amplifier amplifies a signal of one of adjacent global bit lines, and in a second period, each sense amplifier amplifies a signal of the other thereof. Accordingly, coupling between the global bit lines can be suppressed.