发明名称 Logic BIST for system testing using stored patterns
摘要 A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test.
申请公布号 US8473792(B2) 申请公布日期 2013.06.25
申请号 US20110985604 申请日期 2011.01.06
申请人 CHAKRAVARTY SREEJIT;LSI CORPORATION 发明人 CHAKRAVARTY SREEJIT
分类号 G01R31/28 主分类号 G01R31/28
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