发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of suppressing output noise without increasing circuit scale. <P>SOLUTION: A PLL circuit 1 according to the present invention includes: a phase comparator 11 detecting a phase difference between a reference signal Ref and a feedback signal FB; a charge pump 121 outputting a current Ipr according to the detection result of the phase comparator 11; a charge pump 131 outputting a current Iint according to the detection result of the phase comparator 11; a filter 122 outputting a current Iprop in which high frequency components of the output current Ipr of the charge pump 121 is removed; an integrator 132 integrating the output current Iint of the charge pump 131; a voltage-current conversion circuit 133 outputting a current Ivi according to the integration result of the integrator 132; and an oscillator 15 generating an oscillation signal with a frequency according to a current Iro generated by adding the current Iprop and the current Ivi and returning the signal to the phase comparator 11. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013126146(A) 申请公布日期 2013.06.24
申请号 JP20110274560 申请日期 2011.12.15
申请人 RENESAS ELECTRONICS CORP 发明人 KATSUSHIMA AKIO
分类号 H03L7/087;H03K5/26;H03K17/06;H03L7/08;H03L7/093 主分类号 H03L7/087
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