发明名称 Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
摘要 A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.
申请公布号 US2013154108(A1) 申请公布日期 2013.06.20
申请号 US201113326128 申请日期 2011.12.14
申请人 LIN YAOJIAN;CHEN KANG;STATS CHIPPAC, LTD. 发明人 LIN YAOJIAN;CHEN KANG
分类号 H01L21/56;H01L23/48 主分类号 H01L21/56
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