| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress power consumption in a semiconductor device by reducing an excess timing margin while observing a design rule. <P>SOLUTION: A layout device includes a storage device (13) for storing information relating to a layout of a cell and an arithmetic processing unit (12). The arithmetic processing unit executes first processing of determining whether or not a transition constraint and a capacitance constraint on a clock line has a margin and second processing of performing the size reduction or deletion of a clock buffer on the clock line in accordance with the determination result of the first processing. Also, the arithmetic processing unit executes third processing of determining whether or not power can be reduced by the size reduction or deletion of the clock buffer in the second processing and fourth processing of performing the size adjustment of the clock buffer in accordance with the determination result of the third processing. Thus, it is possible to reduce power consumption in a semiconductor device by performing the size reduction or deletion of the clock buffer. <P>COPYRIGHT: (C)2013,JPO&INPIT |
