METHOD AND STRUCTURE FOR FORMING ETSOI CAPACITORS, DIODES, RESISTORS AND BACK GATE CONTACTS

摘要

An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI (20) and BOX (15) layers in a replacement gate HK/MG (80, 85) flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate (27) patterning are achieved by lithography in combination accompanied with appropriate etch.