发明名称 |
METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE |
摘要 |
Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
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申请公布号 |
US2013157451(A1) |
申请公布日期 |
2013.06.20 |
申请号 |
US201113331055 |
申请日期 |
2011.12.20 |
申请人 |
LIN WUU-CHERNG;RICHTER FANGYUN;HSU CHE TA;WU WEN SUN |
发明人 |
LIN WUU-CHERNG;RICHTER FANGYUN;HSU CHE TA;WU WEN SUN |
分类号 |
H01L21/3205;G06F17/50 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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