| 摘要 |
<p>A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.</p> |
