| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a multilayered capacitor that can reduce a voltage variation in the power of a semiconductor chip even if the packaging density of an electrode terminal formed in the semiconductor chip is increased, and to provide a semiconductor package including the same and a method for manufacturing the same. <P>SOLUTION: The multilayered capacitor includes: a plurality of mutually connected first internal electrodes disposed in parallel with a predetermined space; a plurality of mutually connected second internal electrode disposed in parallel with a predetermined space while being mutually interposed with the plurality of first internal electrodes; a first external electrode connected with the plurality of first internal electrodes; and a second external electrode connected with the plurality of second internal electrodes. The plurality of first internal electrodes and the plurality of second internal electrodes are disposed in a region sandwiched between the first external electrode and the second external electrode in such a way that they are almost parallel to the plane which the first external electrode and the second external electrode face. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
