| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce time necessary for an erasing operation by sufficiently using capability of a circuit for generating an erasing voltage of a nonvolatile semiconductor memory device. <P>SOLUTION: A voltage level of an erasing voltage (Vsl) generated by an internal voltage generation circuit (30) is detected by a detection circuit (32). According to its detection result, whether the current supply efficiency of the internal voltage generation circuit is larger than a current amount consumed during cell erasure in a memory mat (10) is determined by a supply efficiency determination circuit (34). According to its determination result, erasure conditions are updated by an erasure condition adjustment part (36). <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
