发明名称 Method and apparatus for efficient inter-thread synchronization for helper threads
摘要 A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.
申请公布号 US8468531(B2) 申请公布日期 2013.06.18
申请号 US20100787810 申请日期 2010.05.26
申请人 GSCHWIND MICHAEL K.;O'BRIEN JOHN K.;SALAPURA VALENTINA;SURA ZEHRA N.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GSCHWIND MICHAEL K.;O'BRIEN JOHN K.;SALAPURA VALENTINA;SURA ZEHRA N.
分类号 G06F9/46;G06F12/08 主分类号 G06F9/46
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