发明名称 |
VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP |
摘要 |
<p>A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has swizzle circuitry to swizzle a vector's elements so as to form a swizzle vector. The logic circuitry also has vector logic circuitry to perform a vector logic operation on said vector and said swizzle vector.</p> |
申请公布号 |
KR20130064794(A) |
申请公布日期 |
2013.06.18 |
申请号 |
KR20137008144 |
申请日期 |
2011.09.24 |
申请人 |
INTEL CORP. |
发明人 |
WIEDEMEIER JEFF;SAMUDRALA SRIDHAR;GOLLIVER ROGER |
分类号 |
G06F9/305;G06F1/00;G06F9/44 |
主分类号 |
G06F9/305 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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