发明名称
摘要 An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
申请公布号 JP2013524383(A) 申请公布日期 2013.06.17
申请号 JP20130504943 申请日期 2011.04.05
申请人 发明人
分类号 G06F12/00;G06F3/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址
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