| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a heterojunction field effect transistor in which increase in gate current leakage and current collapse are minimized and the gate-drain capacitance can be reduced furthermore, and to provide a manufacturing method therefor. <P>SOLUTION: The heterojunction field effect transistor includes a barrier layer 4 formed on a channel layer 3, a cap layer 5 formed on the barrier layer 4 and having a first opening, a dielectric layer 11 having a second opening the size of which is smaller than that of the first opening on the barrier layer 4 in the first opening, a gate electrode 10 having a gate length smaller than the opening size of the first opening but larger than the opening size of the second opening in the first opening, and a source electrode 9 and a drain electrode 8 located, respectively, on one and the other sides of the gate electrode 10. At least the surface of the gate electrode 10 on the drain electrode 8 side is arranged with a space between the cap layer 5. <P>COPYRIGHT: (C)2013,JPO&INPIT |
