发明名称
摘要 <p>A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding WorldID. Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding address space identifier or ASID. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination.</p>
申请公布号 JP2013522775(A) 申请公布日期 2013.06.13
申请号 JP20130500172 申请日期 2011.03.16
申请人 发明人
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
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