| 摘要 |
A debug system includes a debug device and a computer. The debug device includes an SPI reading and writing module, a first control module, a detecting module, and a signal receiving and transmitting module. The computer includes a second control module and a display module. The SPI reading and writing module is connected to an SPI device. The second control module sends an inputted write command to the first control module. The first control module writes data to the SPI device according to the inputted write command. The detecting module sends a fail signal to the first control module after detecting that the data is not written to the SPI device and a written times of the data is greater than a predetermined times. The first control module sends the fail signal to the second control module. The second control module displays the fail signal on the display module.
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