PROCESSING UNIT AND METHOD FOR CONTROLLING PROCESSING UNIT

摘要

The present invention addresses the problem of improving latency degradation associated with an increase in the number of core processors. A processing unit, which is one embodiment of the present invention, comprises: a plurality of processors, each of which performs operations and outputs access requests; a cache memory that holds data resulting from the operations of each of the plurality of processors in cache blocks; a holding unit which holds controlled addresses identifying controlled cache blocks, and controlled identification information representing the processors that are the source of controlled access requests; and a controller which, on the basis of an address to be accessed, which is included in an access request issued by one of the plurality of processors, and request source identification information, which represents the processor that issued the access request, controls an access request for the cache block identified by the controlled address and controlled identification information.