发明名称 Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices
摘要 An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.
申请公布号 US2013147061(A1) 申请公布日期 2013.06.13
申请号 US201313762257 申请日期 2013.02.07
申请人 IO SEMICONDUCTOR, INC.;IO SEMICONDUCTOR, INC. 发明人 ARRIAGADA ANTON;BRINDLE CHRIS;STUBER MICHAEL A.
分类号 H01L21/762;H01L23/522 主分类号 H01L21/762
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