发明名称 |
LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE |
摘要 |
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
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申请公布号 |
US2013147518(A1) |
申请公布日期 |
2013.06.13 |
申请号 |
US201313762430 |
申请日期 |
2013.02.08 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD.;SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
SHIONOIRI YUTAKA;KOBAYASHI HIDETOMO |
分类号 |
H01L29/786;H01L27/088;H03K19/096 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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