PROCESSING UNIT AND METHOD FOR CONTROLLING PROCESSING UNIT

摘要

A processing unit set forth in one aspect of the present invention is provided with: a plurality of processors containing a first cache memory; a second cache memory that holds data resulting from operations performed by each of the plurality of processors; an acquisition unit that acquires attribute information pertaining to the first cache memory, which is to be controlled, of the source of an access request to be controlled, said attribute information containing pathway information representing the pathway of a cache block of the first cache memory; a holding unit that holds address information and the attribute information; and a controller that controls an access request relating to a replacement request for a cache block of a second cache memory specified by address information and attribute information to be controlled, on the basis of an address to be replaced, which is included in an access request relating to a replacement request issued by one of the plurality of processors pertaining to the first cache memory, and pathway information representing the pathway of a cache block to be replaced in the first cache memory.