发明名称 |
Functional unit for vector leading zeroes, vector trailing zeroes, vector operand IS count and vector parity calculation |
摘要 |
A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction. |
申请公布号 |
GB2497455(A) |
申请公布日期 |
2013.06.12 |
申请号 |
GB20130003912 |
申请日期 |
2011.09.23 |
申请人 |
INTEL CORPORATION |
发明人 |
SRIDHAR SAMUDRALA;ROGER A GOLLIVER;ERIC W MAHURIN;JEFF WIEDEMEIER |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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