发明名称 |
Method of forming shielded gate power transistor utilizing chemical mechanical planarization |
摘要 |
A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
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申请公布号 |
US8461040(B2) |
申请公布日期 |
2013.06.11 |
申请号 |
US201113042292 |
申请日期 |
2011.03.07 |
申请人 |
GREBS THOMAS E.;RIDLEY RODNEY S.;KRAFT NATHAN LAWRENCE;FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
GREBS THOMAS E.;RIDLEY RODNEY S.;KRAFT NATHAN LAWRENCE |
分类号 |
H01L21/4763 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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