发明名称 Process for producing a metallization level and a via level and corresponding integrated circuit
摘要 A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.
申请公布号 US8461046(B2) 申请公布日期 2013.06.11
申请号 US201113187326 申请日期 2011.07.20
申请人 VANNIER PATRICK;STMICROELECTRONICS (CROLLES 2) SAS 发明人 VANNIER PATRICK
分类号 H01L21/768 主分类号 H01L21/768
代理机构 代理人
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