Mechanism for a shared serial peripheral interface

摘要

According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.