| 摘要 |
PURPOSE: A cluster system is provided to normally process a clock signal in a transceiver unit of each stage under any circumstances by forcefully compensating a reference pulse width in the corresponding transceiver unit when a pulse width of a clock signal transmitting in an arbitrary transceiver unit. CONSTITUTION: A clock signal loss prevention circuit of a cluster system includes a OR gate(401) OR calculating a compensation pulse input from a controller; a falling edge detector(402) detecting the falling edge of the clock signal input from the OR gate and outputting the falling edge detection signal; a pulse generator(403) generating and outputting a clock signal having a predetermined low pulse width after synchronizing the falling edge detection signal; a rising edge detector(404) detecting the rising edge of the clock signal input from the OR gate and outputting the rising edge detection signal; a compensation pulse generator(405) generating and outputting the compensation signal having a predetermined high pulse width after synchronizing the rising edge detection signal input from the rising edge detector. [Reference numerals] (402) Falling edge detector; (403) Pulse generator; (404) Rising edge detector; (405) Compensation pulse generator |
