发明名称 |
VOLATILE MEMORY ACCESS VIA SHARED BITLINES |
摘要 |
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation. |
申请公布号 |
US2013141992(A1) |
申请公布日期 |
2013.06.06 |
申请号 |
US201113312867 |
申请日期 |
2011.12.06 |
申请人 |
LEE MICHAEL JU HYEOK;TRUONG BAO G.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LEE MICHAEL JU HYEOK;TRUONG BAO G. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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