| 摘要 |
<P>PROBLEM TO BE SOLVED: To acquire an accurate instruction generation timing, when simultaneously executing instructions of trace objects. <P>SOLUTION: A timing information generation circuit 131 outputs timing information representing whether or not output timings of trace data items are the same on the basis of output enable signals of processors 1(2) that are synchronously output with outputs of trace data items from each of a first CPU core 111 and a second CPU core 121. A trace message generation circuit 132 generates a trace message formed by associating each trace data item, a time stamp of when acquiring each trace data item, and the timing information. A trace memory writing control circuit 144 writes the trace message generated by the trace message generation circuit 132 in a trace memory 150. <P>COPYRIGHT: (C)2013,JPO&INPIT |
