| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a latched comparator that implements a high speed reliable latch output without compromising characteristics of a differential circuit. <P>SOLUTION: A latched comparator (1) includes at least either of: a seventh MOS transistor (QN3) having a drain-source path connected between a first node (N1) on a first current path between a first MOS transistor (Q1) and a third MOS transistor (Q3) and a second node (N2) on a second current path between a second MOS transistor (Q2) and a fifth MOS transistor (Q4), and a gate connected to an output of a first CMOS inverter; and an eighth MOS transistor (QN4) having a drain-source path connected between the first node (N1) and the second node (N2) and a gate connected to an output of a second CMOS inverter. <P>COPYRIGHT: (C)2013,JPO&INPIT |
