Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port

摘要

An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.