发明名称 |
FRACTIONAL SPUR REDUCTION USING CONTROLLED CLOCK JITTER |
摘要 |
<p>In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.</p> |
申请公布号 |
EP2599226(A1) |
申请公布日期 |
2013.06.05 |
申请号 |
EP20110813056 |
申请日期 |
2011.07.26 |
申请人 |
MARVELL WORLD TRADE LTD. |
发明人 |
ROMANO, LUCA;VENCA, ALESSANDRO;DAL TOSO, STEFANO;MILANI, ANTONIO;BRUNN, BRIAN |
分类号 |
H03L7/16 |
主分类号 |
H03L7/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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