| 摘要 |
PURPOSE: A dual trigger low energy flip flop circuit is provided to reduce power consumption. CONSTITUTION: Transistors(304,305,306,309,310,311,316,317,322,323,325) are NMOS devices. Transistors(301,302,303,307,308,312,313,314,315,319,320,321) are PMOS devices. A flip flop circuit(300) comprises four main sub-circuits, a reset trigger sub circuit, a set trigger sub circuit, an output buffer, and an AOI(And-Or-Invert) RS(Reset-Set) latch. The transistors(301,302,303,304,305,306,324) and an inverter(327) form the reset trigger sub-circuit. The transistors(301,307,308,309,310,311,325) and an inverter(328) form the set trigger sub-circuit. The transistor(301) is shared between the reset trigger sub-circuit and the set trigger sub-circuit. [Reference numerals] (300) Flip-flop circuit
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