发明名称 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
摘要 A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
申请公布号 US8456922(B2) 申请公布日期 2013.06.04
申请号 US201213477431 申请日期 2012.05.22
申请人 CHEN CHUNG-ZEN;LIN YANG-CHIEH;KUO CHUNG-SHAN;MOSAID TECHNOLOGIES INCORPORATED 发明人 CHEN CHUNG-ZEN;LIN YANG-CHIEH;KUO CHUNG-SHAN
分类号 G11C16/16 主分类号 G11C16/16
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