发明名称 |
Semiconductor device having a pad-disposition restriction area |
摘要 |
Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
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申请公布号 |
US8456024(B2) |
申请公布日期 |
2013.06.04 |
申请号 |
US201213489215 |
申请日期 |
2012.06.05 |
申请人 |
OHNISHI MANABU;TAKEMURA KOJI;NAGAI NORIYUKI;HUH HOYEUN;NAKAYAMA TOMOYUKI;DOI ATSUSHI;PANASONIC CORPORATION |
发明人 |
OHNISHI MANABU;TAKEMURA KOJI;NAGAI NORIYUKI;HUH HOYEUN;NAKAYAMA TOMOYUKI;DOI ATSUSHI |
分类号 |
H01L23/12;H01L23/52;H01L21/60;H01L23/31;H01L23/485;H01L23/50 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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