发明名称 |
Vertical transistor for random-access memory and manufacturing method thereof |
摘要 |
A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.
|
申请公布号 |
US8455319(B2) |
申请公布日期 |
2013.06.04 |
申请号 |
US201113039523 |
申请日期 |
2011.03.03 |
申请人 |
LEE TZUNG HAN;LEE CHUNG-YUAN;LIU HSIEN-WEN;INOTERA MEMORIES, INC. |
发明人 |
LEE TZUNG HAN;LEE CHUNG-YUAN;LIU HSIEN-WEN |
分类号 |
H01L21/336;H01L29/76 |
主分类号 |
H01L21/336 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|