发明名称 Modular multiplier apparatus with reduced critical path of arithmetic operation and method of reducing the critical path of arithmetic operation in arithmetic operation apparatus
摘要 Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation. The modular multiplier apparatus for obtaining a quotient and a result of an arithmetic operation of modular multiplication by using a modulus and two arbitrary constants includes: a reduction unit for obtaining a short path carry (SPC) included when a result of a modular arithmetic operation is obtained at a current stage, by using a medium calculation result; a carry predictor for predicting a long path carry (LPC) included when the result of the modular arithmetic operation is obtained at the current stage, by using the medium calculation result; and an accumulator for accumulating the result of the modular arithmetic operation by using the SPC and the LPC, wherein the medium calculation result is obtained by adding a result of a modular arithmetic operation obtained at a previous stage and a partial product of the two constants obtained at the current stage.
申请公布号 US8458242(B2) 申请公布日期 2013.06.04
申请号 US20100660382 申请日期 2010.02.25
申请人 KIM YOUNG-SIK;NOH MI-JUNG;AHN KYOUNG-MOON;SHIN SUN-SOO;SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM YOUNG-SIK;NOH MI-JUNG;AHN KYOUNG-MOON;SHIN SUN-SOO
分类号 G06F7/72 主分类号 G06F7/72
代理机构 代理人
主权项
地址