| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a signal transfer circuit capable of improving restrictions of timing of an input/output signal between an arbiter performing access according to a protocol and a bus master. <P>SOLUTION: A signal transfer circuit includes: a control signal transfer section, and a data signal transfer section. The control signal transfer section, when relaying an access request to a memory input from a bus master to an arbiter, outputs an access request input signal to be input, an access request output signal in which timing of a memory address input signal is adjusted, and a memory address output signal, and outputs an access permission output signal to the bus master ahead of an access permission input signal input from the arbiter. The data signal transfer section, when relaying data to the bus master or arbiter, outputs each data output signal in which timing of each data input signal to be input is adjusted, to the bus master or arbiter, and outputs a data effective period output signal in which timing of a data effective period input signal input from the arbiter is adjusted, to the bus master. <P>COPYRIGHT: (C)2013,JPO&INPIT |
