| 摘要 |
<p>PURPOSE: A hardware structure of a flash controller used in a flash device is provided to improve the efficiency of a flash bus interface through a unique hardware architecture with a multiple hardware property. CONSTITUTION: A flash media controller(102) includes a dedicated data transmission path, a flash lane controller, and a flash bus controller. The flash lane controller is connected to one or more dedicated data transmission paths. The flash bus controller is connected to the flash lane controller. The flash media controller implements a context with information for a transaction with a flash bank. [Reference numerals] (102) Flash media controller(FMC); (104a,104b,104c,104d,104e,104f,104g,104n,106a,106b,106c,106d,106e,106f,106g,106n) Flash device; (108) FARM processor; (110) Memory controller</p> |
