发明名称 PLANARIZED BUMPS FOR UNDERFILL CONTROL
摘要 The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.
申请公布号 US2013134581(A1) 申请公布日期 2013.05.30
申请号 US201113308162 申请日期 2011.11.30
申请人 LIN JING-CHENG;TSAI PO-HAO;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LIN JING-CHENG;TSAI PO-HAO
分类号 H01L23/498;H01L21/50;H01L21/768 主分类号 H01L23/498
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